1. Field of the Invention
The present invention relates to logic for interfacing between a processor and a plurality of memories having different operating and timing characteristics.
2. Prior Art
It is known in the prior art to provide a single interface controller for a plurality of peripheral devices such as storage devices and input/output devices. However, prior art interface controllers are limited to the selection of devices of the same type each of which contains its own timing generator. The controller thus acts as a peripheral processor, interpreting instructions from the central processor and selecting the desired one of the plurality of devices under its control. This type of control system is wasteful of circuitry in that timing and control circuits must be duplicated for each device.